Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Non-volatile memory is memory that can retain its data values for some extended period without the application of power. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage of the cells, through programming (which is sometimes referred to as writing) of charge-storage structures (e.g., floating gates or charge traps) or other physical phenomena (e.g., phase change or polarization), determine the data value of each cell. Common uses for flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones, and removable memory modules, and the uses for non-volatile memory continue to expand.
A NAND flash memory device is a common type of flash memory device, so called for the logical form in which the basic memory cell configuration is arranged. Typically, the array of memory cells for NAND flash memory devices is arranged such that the control gate of each memory cell of a row of the array is connected together to form an access line, such as a word line. Columns of the array include strings (often termed NAND strings) of memory cells connected together in series, source to drain, between a pair of select lines, a source select line and a drain select line.
A “column” refers to a group of memory cells that are commonly coupled to a local data line, such as a local bit line. It does not require any particular orientation or linear relationship, but instead refers to the logical relationship between memory cell and data line. The source select line includes a source select gate at each intersection between a NAND string and the source select line, and the drain select line includes a drain select gate at each intersection between a NAND string and the drain select line. Each source select gate is connected to a source line, while each drain select gate is connected to a data line, such as column bit line.
In order for memory manufacturers to remain competitive, memory designers are constantly trying to increase the density of memory devices. Increasing the density of a flash memory device generally requires reducing spacing between memory cells and/or making memory cells smaller. Smaller dimensions of some device elements may cause operational problems with the cell.
One way of increasing the density of memory devices is to form stacked memory arrays, e.g., often referred to as three-dimensional memory arrays. For example, one type of three-dimensional memory array may include pillars of stacked memory elements, such as substantially vertical NAND strings.
FIG. 1A is a cross-sectional view of a portion of a memory array of the prior art that includes a substantially vertical string of memory cells 110 (e.g., memory cells 110B to 110T coupled in series) located adjacent to a substantially vertical semiconductor pillar 120 that may act as channel region for the substantially vertical string of memory cells 110. For example, during operation of one or more memory cells 110 of the string, a channel can be formed in the semiconductor pillar 120.
FIGS. 1B and 1C respectively show cross-sections of memory cells 110T and 110B located at different levels (e.g., vertical levels) within the memory array (e.g., within the string). For example, memory cell 110T is located at a vertical level (e.g., near the top of the memory array) that is above a vertical level (e.g., near the bottom of the memory array) at which memory cell 110B is located.
Each memory cell 110 may have a charge-storage structure (e.g., that may be a conductive floating gate, a dielectric charge trap, etc). For example, memory cell 110T may have a charge-storage structure 130T, and memory cell 110B may have a charge-storage structure 130B. Each memory cell 110 may have a tunnel dielectric 135 interposed between its charge-storage structure 130 and pillar 120. For example, memory cell 110T may have a tunnel dielectric 135T interposed between charge-storage structure 130T and pillar 120, and memory cell 110B may have a tunnel dielectric 135B interposed between charge-storage structure 130B and pillar 120. Each memory cell 110 may have a control gate 140 (e.g., as a portion of or coupled to access lines, such as word lines). For example, memory cells 110T and 110B may respectively include control gates 140T and 140B. Each memory cell 110 may have dielectrics 145 and 150 interposed between its charge-storage structure 130 and control gate 140.
Semiconductor pillar 120 may be tapered in a direction from top to bottom, causing the size of, such as the cross-sectional area and/or the perimeter of, semiconductor pillar 120 to be smaller at memory cell 110B near the bottom of the memory array than the size of, such as the cross-sectional area and/or the perimeter of, semiconductor pillar 120 at memory cell 110T near the top of the memory array, as shown in FIGS. 1A-1C. The cross-sectional area and/or the outer perimeter of charge-storage structure 130B where the pillar 120 has a smaller cross-sectional area and perimeter may be smaller than the cross-sectional area and/or the outer perimeter of charge-storage structure 130T where the pillar 120 has a larger cross-sectional area and perimeter.
The cross-sectional area may be defined as the area of a cross-section that is substantially perpendicular to (e.g., that is perpendicular to) the longitudinal central axis 152, e.g., that may be substantially vertical, of pillar 120. For example, the cross-sectional areas of pillar 120 and charge-storage structures 130 are respectively the areas of the cross-sections of pillar 120 and the charge-storage structures 130 shown in FIGS. 1B and 1C.
Semiconductor pillar 120, the charge-storage structures 130, the tunnel dielectrics 145, and the dielectrics 145 and 150 are sometimes formed in an opening formed though a material, such as alternating dielectrics and conductors, e.g., that form the control gates 140, and therefore may take on the overall shape of the openings. In some instances, the process, e.g., etching, that forms the opening results in an opening that tapers in a direction from top to bottom, thereby causing the cross-sectional area of semiconductor pillar 120, the cross-sectional areas of charge-storage structures 130, the cross-sectional areas of tunnel dielectrics 145, and the cross-sectional areas of the dielectrics 145 and 150 to decrease in a direction from top to bottom of the array.
The difference in the cross-sectional areas of the pillar 120 at memory cells 110T and 110B and/or the difference in the cross-sectional areas of the charge-storage structures 130 of memory cells 110T and 110B can cause differences in the programming and erase properties of memory cells 110T and 110B. This means that the programming and erase properties of the memory cells may vary over the height of the string of memory cells. For example, the channel capacitance at memory cell memory cell 110B might be less than the channel capacitance at memory cell 110T, resulting in memory cell 110B programming and erasing more quickly than memory cell 110T.
The number of electrons that can be stored in charge-storage structure 130B of memory cell 110B may be less than the number of electrons that can be stored in charge-storage structure 130T of memory cell 110T. This can cause memory cell 110B to have a shorter retention time than memory cell 110T, and thus wider threshold voltage ranges for given program levels than memory cell 110T. For example, the loss or gain of an electron in charge-storage structure 130B may produce a larger change in the threshold voltage of memory cell 110B than the loss or gain of an electron in charge-storage structure 130T on the threshold voltage of memory cell 110T.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternatives to existing memory arrays with pillars of stacked memory elements.